The Future of Learning is Blended

Chapter of the following book: Moving Horizontally: The New Dimensions of At-Scale Learning at the Time of COVID-19, edited by Yakut Gazi and Nelson BakerThe adoption of online learning within universities has been sporadic and rare. However, with the onset of COVID-19, higher ed institutions worldwide have been forced to switch from inperson to online learning. This transition, while challenging, is dramatically increasing the adoption of online learning in higher education. However, for online learning to endure, it must be integrated across the entire campus, or in other words, it must truly scale horizontally. Blended learning, which allows universities to integrate online learning with in-person learning, provides the best of the two learning models and offers a much lower resistance path to campus-wide adoption. Blended learning increases business continuity and has unique pedagogical benefits which increase learning outcomes. It is the future of higher education

The Case for a Factored Operating System (fos)

The next decade will afford us computer chips with 1,000 - 10,000 cores on a single piece of silicon. Contemporary operating systems have been designed to operate on a single core or small number of cores and hence are not well suited to manage and provide operating system services at such large scale. Managing 10,000 cores is so fundamentally different from managing two cores that the traditional evolutionary approach of operating system optimization will cease to work. The fundamental design of operating systems and operating system data structures must be rethought. This work begins by documenting the scalability problems of contemporary operating systems. These studies are used to motivate the design of a factored operating system (fos). fos is a new operating system targeting 1000+ core multicore systems where space sharing replaces traditional time sharing to increase scalability. fos is built as a collection of Internet inspired services. Each operating system service is factored into a fleet of communicating servers which in aggregate implement a system service. These servers are designed much in the way that distributed Internet services are designed, but instead of providing high level Internet services, these servers provide traditional kernel services and manage traditional kernel data structures in a factored, spatially distributed manner. The servers are bound to distinct processing cores and by doing so do not fight with end user applications for implicit resources such as TLBs and caches. Also, spatial distribution of these OS services facilitates locality as many operations only need to communicate with the nearest server for a given service

Anatomy of a message in the Alewife multiprocessor

Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is often implemented with a layer of interpretive hardware on top of a message-passing communications network. This interpretive layer is responsible for data location, data movement, and cache coherence. It uses patterns of communication that benefit common programming styles, but which are only heuristics. This suggests that certain styles of communication may benefit from direct access to the underlying communications substrate. The Alewife machine, a shared-memory multiprocessor being built at MIT, provides such an interface. The interface is an integral part of the shared memory implementation and affords direct, user-level access to the network queues, supports an efficient DMA mechanism, and includes fast trap handling for message reception. This paper discusses the design and implementation of the Alewife message-passing interface and addresses the issues and advantages of using such an interface to complement hardware-synthesized shared memory.National Science Foundation (U.S.) (Grant MIP-9012773)United States. Defense Advanced Research Projects Agency (Contract N00014-87-K-0825

El Plan Estratégico 2016-2021 abre un canal de participación a la comunidad universitaria

Audiovisuales: Entrevista a Anant Agarwal disponible en: https://youtu.be/1E-4vK1wK8wEl Plan Estratégico 2016-2021 de la UC3M es el instrumento que define la hoja de ruta de la universidad para los próximos cinco años. El plan constituye un marco general de actuación para llevar a cabo acciones que influyan en todas las unidades que integran la universidad: centros, departamentos, institutos, servicios o grupos de investigación. Todo con el fin de seguir avanzando en el objetivo de situar a la UC3M entre las mejores universidades europeas.Contiene: Entrevista a Anant Agarwal (p. 13) . -- Entrevista a Carlos Delgado Kloos (pp. 16-17)

Remote Store Programming: Mechanisms and Performance

This paper presents remote store programming (RSP). This paradigm combines usability and efficiency through the exploitation of a simple hardware mechanism, the remote store, which can easily be added to existing multicores.Remote store programs are marked by fine-grained and one-sided communication which results in a stream of data flowing from the registers of a sending process to the cache of a destination process. The RSP model and its hardware implementation trade a relatively high store latency for a low load latency because loads are more common than stores, and it is easier to tolerate store latency than load latency. This paper demonstrates the performance advantages of remote store programming by comparing it to both cache-coherent shared memory and direct memory access (DMA) based approaches using the TILEPro64 processor. The paper studies two applications: a two-dimensional Fast Fourier Transform (2D FFT) and an H.264 encoder for high-definition video. For a 2D FFT using 56 cores, RSP is 1.64x faster than DMA and 4.4x faster than shared memory. For an H.264 encoder using 40 cores, RSP achieves the same performance as DMA and 4.8x the performance of shared memory. Along with these performance advantages, RSP requires the least hardware support of the three. RSP's features, performance, and hardware simplicity make it well suited to the embedded processing domain